Complementary PWM

Complementary 0/1 gate signals at a fixed frequency and duty cycle. Ideal simultaneous switching, with no dead time.

  • signal
  • Gradara equations
  • 2 ports
  • 2 parameters
BlockComplementary PWMKindpwmPairLibraryControl

Description

Generates two complementary gate signals at a fixed switching frequency and duty cycle. high is 1 for the first duty fraction of each period and 0 for the rest; low is always its complement.

Use it to drive the two switches of a half bridge, such as the high-side and low-side switches of a buck converter.

Example

Buck converter · Ideal switches 24 V synchronous buck: complementary ideal switches at 10 kHz and 50% duty, 1 mH / 100 µF filter, 10 Ω load. Start from zero stored energy. Expect approximately 12 V and 1.2 A after settling. No losses, dead time, or parasitics.

24 V supplyGate driveHigh-side switchLow-side switch1 mH inductorInductor current100 µF capacitor10 Ω loadOutput voltageGround
In Gradara, select a Complementary PWM block and press F1, then choose Open example. It opens as a new model in My models, ready to run.

Also in this example:DC voltageIdeal switchVoltage sensorCurrent sensorGroundResistorCapacitorInductor

Ports

Outputs 2

  • hihighsignal

    High-side gate signal, 0 or 1. Starts at 1 at t = 0.

  • lolowsignal

    Low-side gate signal, 1 − high.

Parameters

  • Frequencyfrequency10000 Hz

    1 to 1000000

    Switching frequency, in hertz, from 1 Hz to 1 MHz. The period is 1/frequency.

  • Duty cycleduty0.5

    0 to 1

    Fraction of each period that high is 1, from 0 to 1.

Equations

Modelica
T = 1/frequency
high = 1 when (t mod T) < duty · T, otherwise 0
low = 1 − high

Implementation

The block’s Modelica model
Modelica.Blocks.Sources.BooleanPulse pulse(width=100*duty, period=1/frequency);
high = if pulse.y then 1 else 0;
low = 1 - high;

Assumptions and limitations

  • Both outputs switch at the same instant, with no dead time, rise time, or switching delay.
  • Frequency and duty are fixed during a run. For a duty cycle driven by a signal, use PWM generator.
  • Pulses begin at t = 0; there is no start delay or phase offset.

Tips

  • The pulse comes from the MSL BooleanPulse with width = 100 · duty %. That source declares a pulse width greater than 0, so duty = 0 lies outside its stated range; use a small positive duty instead.
  • Every edge is a simulation event. A high frequency over a long run means many events and a slower simulation.

Used in

These larger examples use it too. Open them from Examples in the app.

  • Buck converter · Ideal switches

See also

Select a block in Gradara and press F1 to open its page offline.