RS flip-flop

Set/reset latch.

  • Boolean
  • Modelica Standard Library
  • 4 ports
BlockRS flip-flopKindrsFlipFlopLibraryLogic

Description

A set/reset latch built from two cross-coupled NOR gates. S sets Q true, R resets it, and with both false Q keeps its value.

Q starts false and Q̄ starts true.

Example

Latch, timer, and sampler Start and stop buttons set and reset a flip-flop, which times the run, gates a signal, and samples the start time.

EnableStartStopEnabled startStart edgeStop edgeRunningRun timeSine 1 Hz0Gated sineClockStart time
In Gradara, select a RS flip-flop block and press F1, then choose Open example. It opens as a new model in My models, ready to run.

Also in this example:ConstantSine waveClockANDSwitch (logic)TimerBoolean constantBoolean stepTriggered samplerRising edge

Ports

Inputs 2

  • SBoolean

    Set input.

  • RBoolean

    Reset input.

Outputs 2

  • QBoolean

    Latched output.

  • Q̄QIBoolean

    Q̄, normally the complement of Q.

Equations

Modelica
Q = ¬(R ∨ QI)
QI = pre(¬(S ∨ Q)), with pre(…) = true at t = 0
pre(…) breaks the algebraic loop; the latch settles within the event iteration at the same instant.

Implementation

Modelica Standard Library 4.1.0Modelica.Blocks.Logical.RSFlipFlop
MSL documentation

Assumptions and limitations

  • With S and R both true, Q and QI are both false, so QI is not the complement of Q in that state.
  • No propagation delay, setup, or hold times.

See also

Select a block in Gradara and press F1 to open its page offline.