Zero-order hold

Sample and hold.

  • signal
  • Gradara equations
  • 2 ports
  • 1 parameter
BlockZero-order holdKindzohLibraryDiscrete

Description

Samples its input every Ts seconds and holds the value until the next sample. Use it to model an ADC or a sampled controller input.

Example

Sampling A sine held, delayed by one sample, and a step summed at a fixed sample rate.

Sine 1 HzHold 0.1 sUnit delay 0.1 sStepDiscrete integrator
In Gradara, select a Zero-order hold block and press F1, then choose Open example. It opens as a new model in My models, ready to run.

Also in this example:StepSine waveUnit delayDiscrete integrator

Ports

Inputs 1

  • usignal

    Input signal, read at each sample instant.

Outputs 1

  • ysignal

    Output signal, the last sample, constant between samples.

Parameters

  • Sample periodTs0.001 s

    ≥ 0.0001

    Sample period, in seconds. At least 0.0001 s (default 1 ms).

Equations

Modelica
At t = k · Ts, k = 0, 1, 2, …: y = u(t)
Between samples, y holds its value.

Implementation

The block’s Modelica model
when sample(0, Ts) then
  y = u;
end when;

Assumptions and limitations

  • Samples are taken at fixed multiples of Ts from time 0. No quantization is modeled.

See also

Select a block in Gradara and press F1 to open its page offline.