Less than
True while u1 < u2.
- signal
- Boolean
- Modelica Standard Library
- 3 ports
lessLibraryLogicDescription
Compares two signals: true while u1 is strictly less than u2.
Example
Comparators A sine compared with thresholds, with a ramp, and through a hysteresis band.
sin(πt)t / 4Above 0.5Below −0.5Hysteresis ±0.5Sine > rampSine < ramp
Also in this example:RampSine waveGreater than thresholdLess than thresholdGreater thanHysteresis
Ports
Inputs 2
-
u1
First Real input.
-
u2
Second Real input, in the same units as u1.
Outputs 1
-
y
True while u1 < u2.
Equations
Modelica
y = u1 < u2
Implementation
Modelica Standard Library 4.1.0
MSL documentation Modelica.Blocks.Logical.LessAssumptions and limitations
- No hysteresis; equal inputs give false.
See also
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