NMOS transistor

Shichman–Hodges N-channel MOSFET.

  • electrical
  • Modelica Standard Library
  • 4 ports
  • 2 parameters
BlockNMOS transistorKindnmosLibrarySemiconductors

Description

An N-channel MOSFET using a simplified Shichman–Hodges (level 1) model with a body effect. Drain and source are interchangeable: the lower-potential terminal acts as the source.

The fixed process parameters describe a small integrated device carrying microamperes to milliamperes, not a power MOSFET.

Example

Transistor switches A CMOS inverter of an NMOS and a PMOS transistor, and NPN and PNP transistors switching loads.

InputGround (Input)VDD 5 VGround (VDD 5 V)PMOSNMOSGround (NMOS)Inverter outGround (out)Input, NPNGround (Input, NPN)VCC 5 VGround (VCC 5 V)R C 1 kΩR B 10 kΩNPNGround (NPN)CollectorGround (collector)Input, PNPGround (Input, PNP)VCC 5 V, PNPGround (VCC 5 V, PNP)R B 10 kΩ (PNP)PNPLoad 1 kΩGround (PNP load)Load voltageGround (load voltage)
In Gradara, select a NMOS transistor block and press F1, then choose Open example. It opens as a new model in My models, ready to run.

Also in this example:DC voltageVoltage sensorGroundResistorPulse voltagePMOS transistorNPN transistorPNP transistor

Ports

Conserving terminals 4

  • Delectrical

    Drain.

  • Gelectrical

    Gate. Draws no current.

  • Selectrical

    Source.

  • Belectrical

    Bulk (body). Draws no current; it only shifts the threshold. Usually tied to S or the lowest potential.

Parameters

  • WidthW0.00002 m

    ≥ 0

    Channel width, in meters. Must exceed 2.5 µm, since the effective width is W − 2.5 µm.

  • LengthL0.000006 m

    ≥ 0

    Channel length, in meters. Must exceed 1.5 µm, since the effective length is L − 1.5 µm.

Equations

Modelica
us = min(D.v, S.v), uds = |D.v − S.v|, ubs = min(B.v − us, 0)
β = Beta · (W + dW) / (L + dL)
ugst = (G.v − us − Vt + K2 · ubs) · K5
id = uds / RDS, for ugst ≤ 0
id = β · uds · (ugst − uds / 2) + uds / RDS, for ugst > uds
id = β · ugst² / 2 + uds / RDS, otherwise
Fixed: Beta = 41 µA/V², Vt = 0.8 V, K2 = 1.144, K5 = 0.7311, dW = −2.5 µm, dL = −1.5 µm, RDS = 10 MΩ

Implementation

Modelica Standard Library 4.1.0Modelica.Electrical.Analog.Semiconductors.NMOS
MSL documentation

Assumptions and limitations

  • Static model: no gate, junction, or overlap capacitances, so no switching transients. No body diode, and no temperature dependence.

Tips

  • For a power switch driven by a Boolean, use GTO thyristor or Switch (Boolean) instead.

See also

Select a block in Gradara and press F1 to open its page offline.