Discrete integrator

Sampled integrator accumulating the current input at each sample.

  • signal
  • Gradara equations
  • 2 ports
  • 1 parameter
BlockDiscrete integratorKinddiscreteIntegratorLibraryDiscrete

Description

A sampled integrator. At each sample instant it adds Ts times the current input to its state, a backward-Euler sum.

Example

Sampling A sine held, delayed by one sample, and a step summed at a fixed sample rate.

Sine 1 HzHold 0.1 sUnit delay 0.1 sStepDiscrete integrator
In Gradara, select a Discrete integrator block and press F1, then choose Open example. It opens as a new model in My models, ready to run.

Also in this example:StepSine waveUnit delayZero-order hold

Ports

Inputs 1

  • usignal

    Input signal, read at each sample instant.

Outputs 1

  • ysignal

    Output signal, the accumulated sum, held between samples.

Parameters

  • Sample periodTs0.001 s

    ≥ 0.0001

    Sample period, in seconds. At least 0.0001 s (default 1 ms).

Equations

Modelica
At t = k · Ts, k = 0, 1, 2, …:
x[k] = x[k − 1] + Ts · u[k], with x = 0 before the first sample
y = x

Implementation

The block’s Modelica model
discrete Real x(start=0, fixed=true);
when sample(0, Ts) then
  x = pre(x) + Ts*u;
end when;
y = x;

Assumptions and limitations

  • No output limits, reset, or initial-value setting. The state starts at 0.
  • Samples are taken at fixed multiples of Ts from time 0.

See also

Select a block in Gradara and press F1 to open its page offline.